Package: verilator (4.010-1)

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Homepage [www.veripool.org]

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Hurtig og fri Verilog-simulator

Verilator er den hurtigste frie Verilog HDL-simulator, og den slår mange kommercielle simulatorer. Den kompilerer synthesizer egnet Verilog (ikke test-bench-kode!), samt lidt PSL, SystemVerilog- og Synthesis-påstande til C++ eller SystemC-kode. Det er designet for store projekter, hvor hurtig simuleringsydelse er af primær koncern, og er specielt velegnet til at oprette kørbare modeller for CPU'er for indlejrede programdesignhold.

Tags: Field: Electronics, Implemented in: C++, implemented-in::perl, interface::commandline, Role: Program, Purpose: Simulating

Other Packages Related to verilator

depends

recommends

suggests

enhances

dep: libc6 (>= 2.14) [amd64]

GNU C-bibliotek: Delte biblioteker
also a virtual package provided by libc6-udeb

dep: libc6 (>= 2.17) [arm64]

dep: libc6 (>= 2.28) [armhf, i386]
dep: libgcc1 (>= 1:3.0) [amd64, arm64]

GCC støttebibliotek

dep: libgcc1 (>= 1:3.5) [armhf]

dep: libgcc1 (>= 1:4.2) [i386]
dep: libstdc++6 (>= 5.2)

GNU Standard C++ bibliotek v3

rec: libsystemc-dev

Udviklingsfiler for SystemC-biblioteket

sug: gtkwave

Fremviser for filer i VCD-waveform (Value Change Dump)

Download verilator

Download for all available architectures
Architecture	Package Size	Installed Size	Files
amd64	3,465.5 kB	16,893.0 kB	[list of files]
arm64	3,116.5 kB	16,505.0 kB	[list of files]
armhf	2,891.3 kB	10,574.0 kB	[list of files]
i386	3,634.7 kB	15,056.0 kB	[list of files]