Пакети в „experimental“, Под-раздел electronics

gnucap (1:20230520-dev-1+b1)

GNU Circuit Analysis package, main executable

gnucap-common (1:20230520-dev-1)

GNU Circuit Analysis package, development headers

gnucap-default-plugins0 (1:20230520-dev-1+b1)

GNU Circuit Analysis package, default plugins

qflow (1.4.62+dfsg.1-1~exp1) [debports]

Open-Source Digital Synthesis Flow

yosys (0.33-6~exp2+b1 [armel, armhf, m68k, riscv64, sh4], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, x32])

Framework for Verilog RTL synthesis

yosys-abc (0.33-6~exp2+b1 [armel, armhf, m68k, riscv64, sh4], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, x32])

Sequential Logic Synthesis and Verification Algorithms

yosys-dev (0.33-6~exp2+b1 [armel, armhf, m68k, riscv64, sh4], 0.33-6~exp2 [alpha, amd64, arm64, i386, mips64el, ppc64el, x32])

Framework for Verilog RTL synthesis (development files)