套件：opensta-dev（0~20191111gitc018cb2+dfsg-1）

Gate-level Static Timing Analyzer - development files

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

This package contains the header files and some libraries for development.

標籤: 軟體開發: 函式庫, 角色: 開發用函式庫

本頁其他語言版本如下（如何設定預設文件語言）：