[ 原始碼： opensta ]
套件：opensta（0~20191111gitc018cb2+dfsg-1）
opensta 的相關連結
Debian 的資源：
下載原始碼套件 opensta：
- [opensta_0~20191111gitc018cb2+dfsg-1.dsc]
- [opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz]
- [opensta_0~20191111gitc018cb2+dfsg-1.debian.tar.xz]
維護小組：
外部的資源：
- 主頁 [github.com]
相似套件：
Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
其他與 opensta 有關的套件
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- dep: libc6 (>= 2.29)
- GNU C 函式庫：共用函式庫
同時作為一個虛擬套件由這些套件填實： libc6-udeb
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- dep: libgcc1 (>= 1:3.5)
- 套件暫時不可用
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- dep: libreadline8 (>= 6.0)
- GNU readline 與 history 函式庫，執行時期函式庫
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- dep: libstdc++6 (>= 6)
- GNU Standard C++ Library v3
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- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
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- dep: zlib1g (>= 1:1.1.4)
- 壓縮函式庫 - 跑程式時用(runtime)