Functional hardware description language - library

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

 * Strongly typed, but with a very high degree of type inference, enabling both

safe and fast prototyping using concise descriptions.

 * Interactive REPL: load your designs in an interpreter and easily test all

your component without needing to setup a test bench.

 * Higher-order functions, with type inference, result in designs that are

fully parametric by default.

 * Synchronous sequential circuit design based on streams of values, called

@Signal@s, lead to natural descriptions of feedback loops.

 * Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

 * The CoreHW internal language: SystemF + Letrec + Case-decomposition

 * The normalisation process that brings CoreHW in a normal form that can be

converted to a netlist

 * Blackbox/Primitive Handling

Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:

 * <https://hackage.haskell.org/package/clash-ghc GHC/Haskell Frontend>

 * <https://github.com/christiaanb/Idris-dev Idris Frontend>

Prelude library: <https://hackage.haskell.org/package/clash-prelude>

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