[ 源代码： yosys ]
软件包：yosys-abc（0.52-2）
yosys-abc 的相关链接
Debian 的资源：
下载源码包 yosys：
- [yosys_0.52-2.dsc]
- [yosys_0.52.orig-abc.tar.gz]
- [yosys_0.52.orig.tar.gz]
- [yosys_0.52-2.debian.tar.xz]
维护小组：
外部的资源：
- 主页 [github.com]
相似软件包：
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in the yosys RTL synthesis framework.
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