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[ 源代码: covered  ]

软件包:covered(0.7.10-3 以及其他的)

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

标签: 领域: 电子学, 实做语言: C, 用户接口: interface::commandline, interface::graphical, X 窗口系统, 角色: 程序, 界面工具箱: uitoolkit::tk, use::viewing, X 窗口系统: 应用程序

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下载可用于所有硬件架构的
硬件架构 版本 软件包大小 安装后大小 文件
amd64 0.7.10-3+b1 531.1 kB2,394.0 kB [文件列表]
arm64 0.7.10-3+b1 433.3 kB2,254.0 kB [文件列表]
armhf 0.7.10-3+b1 461.0 kB1,813.0 kB [文件列表]
i386 0.7.10-3+b1 536.5 kB2,537.0 kB [文件列表]