[ 源代码： verilator ]
软件包：verilator（4.010-1）
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
其他与 verilator 有关的软件包
|
|
|
|
-
- dep: libc6 (>= 2.14)
- GNU C 语言运行库：共享库
同时作为一个虚包由这些包填实： libc6-udeb
-
- dep: libgcc1 (>= 1:3.0)
- GCC 支持库
-
- dep: libstdc++6 (>= 5.2)
- GNU 标准 C++ 库，第3版
-
- rec: libsystemc-dev
- Development files for SystemC library
-
- sug: gtkwave
- VCD (Value Change Dump) file waveform viewer