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[ 源代码: verilator  ]

软件包:verilator(4.010-1)

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fast free Verilog simulator

Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

标签: 领域: 电子学, 实做语言: C++, implemented-in::perl, interface::commandline, 角色: 程序, Purpose: 仿真

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下载可用于所有硬件架构的
硬件架构 软件包大小 安装后大小 文件
amd64 3,465.5 kB16,893.0 kB [文件列表]