[ 源代码： opensta ]
软件包：opensta（0~20191111gitc018cb2+dfsg-1）
opensta 的相关链接
Debian 的资源：
下载源码包 opensta：
- [opensta_0~20191111gitc018cb2+dfsg-1.dsc]
- [opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz]
- [opensta_0~20191111gitc018cb2+dfsg-1.debian.tar.xz]
维护小组：
外部的资源：
- 主页 [github.com]
相似软件包：
Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
其他与 opensta 有关的软件包
|
|
|
|
-
- dep: libc6 (>= 2.29)
- GNU C 语言运行库：共享库
同时作为一个虚包由这些包填实： libc6-udeb
-
- dep: libgcc1 (>= 1:3.5)
- 软件包暂时不可用
-
- dep: libreadline8 (>= 6.0)
- GNU readline 与 history 库，运行时
-
- dep: libstdc++6 (>= 6)
- GNU 标准 C++ 库，第3版
-
- dep: libtcl8.6 (>= 8.6.0)
- Tcl (the Tool Command Language) v8.6 - run-time library files
-
- dep: zlib1g (>= 1:1.1.4)
- 压缩库 - 运行时