Package: iverilog (12.0-2 and others)

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Homepage [iverilog.icarus.com]

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Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

Tags: Field: Elektronika, Implemented in: C++, User Interface: interface::commandline, role::program

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Download iverilog

Download for all available architectures
Architecture	Version	Package Size	Installed Size	Files
amd64	12.0-2+b1	1,998.1 kB	7,022.0 kB	[list of files]