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[ Source: covered  ]

Package: covered (0.7.10-4)

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Verilog code coverage analysis tool

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Tags: Field: Electronics, Implemented in: C, User Interface: interface::commandline, interface::graphical, X Window System, Role: Program, Interface Toolkit: uitoolkit::tk, use::viewing, X Window System: Application

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Architecture Package Size Installed Size Files
mips64el 444.8 kB2,647.0 kB [list of files]