Package: verilator (5.024-1 and others) [debports]
Links for verilator
Debian Resources:
Download Source Package :
Not foundMaintainers:
External Resources:
- Homepage [www.veripool.org]
Similar packages:
fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
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Download verilator
| Architecture | Version | Package Size | Installed Size | Files |
|---|---|---|---|---|
| hppa (unofficial port) | 5.024-1+b2 | 1,405.2 kB | 4,191.0 kB | [list of files] |