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Package: opensta (0~20191111gitc018cb2+dfsg-1)

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Gate-level Static Timing Analyzer

After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.

It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.

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Download for all available architectures
Architecture Package Size Installed Size Files
mips64el 830.0 kB5,310.0 kB [list of files]